What are we trying to do?
We want to create a GPS correlator in a programmable logic device, like FPGA or CPLD, for embedded use. This means that the receiver must:
- be lower power (on order 1-2 W)
- be small (< 10 x 10 cm)
- be easily integratable with an external microcontroller/flight computer
There's probably a "right" way to about this: we read the blue book specs on receivers, and we start from those first principles to create the logic design. However, we're lazy, and we want to get this done, so we'll take the same route everyone takes when they do this :) - we'll recreate the Zarlink GP2021 in some kind of HDL.
Note that this is the same route that the UNSW SNAP folks took in their Namuru GPS receiver.
What parts of the GP2021 do we really need?
Looking at the block diagram on page of the GP2021 datasheet, we need (including inputs and outputs):
- The GPS 12-channel correlator (all of Figure 4, with each channel being Figure 5)
MAG(in "Real_Input" mode)
- Some clock circuitry
CLK_T(40 MHz from RF front end),
CLK_I('inverted' 40 MHz from RF front end)
SAMPCLK(40/7 MHz clock output with 4:3 ratio to RF front end)
- Probably a bit of power and reset control
- Some kind of microcontroller interface
We absolutely don't need:
- Timemark (1 pps) (although possibly we'll want this later)
- The real time clock
- The serial ports
- A fancy microcontroller interface
- Discrete I/O
We can name them the same as in the GP2021 block diagram: in Figure 4:
- Inputs: from
ACCUM_INT(505.05 us) and
MEAS_INT(99999.90 us) 1
- See Figure 5. What can we throw out here? Probably nothing.
C/A_CODE_GENERATOR, which has a
CODE_PHASE_COUNTER, and an
CARRIER_DCO, which has a
- A bunch of multipliers
- 4x 16 bit accumulators (
Q_TRACKING) (Possibly another 2x:
- Inputs: from