The GPL-GPS Project/ plgplgps

What are we trying to do?

We want to create a GPS correlator in a programmable logic device, like FPGA or CPLD, for embedded use. This means that the receiver must:

  1. be lower power (on order 1-2 W)
  2. be small (< 10 x 10 cm)
  3. be easily integratable with an external microcontroller/flight computer

There's probably a "right" way to about this: we read the blue book specs on receivers, and we start from those first principles to create the logic design. However, we're lazy, and we want to get this done, so we'll take the same route everyone takes when they do this :) - we'll recreate the Zarlink GP2021 in some kind of HDL.

Note that this is the same route that the UNSW SNAP folks took in their Namuru GPS receiver.

What parts of the GP2021 do we really need?

Looking at the block diagram on page of the GP2021 datasheet, we need (including inputs and outputs):

We absolutely don't need:

Functional Blocks

We can name them the same as in the GP2021 block diagram: in Figure 4:

  1. CLOCK_GENERATOR
    • Inputs: CLK_T, CLK_I
    • Outputs: SAMPCLK and internal MULTIPHASE_CLOCKS
  2. TIMEBASE_GENERATOR
    • Inputs: from CLOCK_GENERATOR (MULTIPHASE_CLOCKS)
    • Outputs: ACCUM_INT (505.05 us) and MEAS_INT (99999.90 us) 1 TRACKING_MODULE0 - 11
    • See Figure 5. What can we throw out here? Probably nothing.
    • C/A_CODE_GENERATOR, which has a CODE_SLEW register, a CODE_DCO, a CODE_PHASE_COUNTER, and an EPOCH_COUNTER.
    • CARRIER_DCO, which has a CARRIER_CYCLE_COUNTER
    • A bunch of multipliers
    • 4x 16 bit accumulators (I_PROMPT, Q_PROMPT, I_TRACKING, Q_TRACKING) (Possibly another 2x: I_EARLY, Q_EARLY)